PACE: Power-Aware Computing Engines
Rethinking the hardware-software interface for power-aware
computing
Computer Architecture Group
MIT Laboratory for Computer Science
The PACE research project is sponsored by
DARPA through the Air Force Research
Laboratory under Award Number F30602-00-2-0562
Project Overview
The goal of the PACE project is to develop new energy-efficient
microprocessor architectures that combine high performance with low
power dissipation. Modern instruction set architectures (ISAs), such
as RISC and VLIW machines, provide a hardware-software interface
designed solely for maximum performance with minimum hardware
complexity. Compared with application-specific custom circuitry,
these general purpose processors exhibit a factor of 100-1000 worse
energy-delay product.
We intend to reduce this gap by re-examining the hardware-software
interface, only now considering both performance and energy
consumption. Our approach will be to co-develop new machine
architectures that expose energy-consumption to software together with
new compilation technology that can communicate energy-saving
compile-time knowledge to the hardware. We hope to achieve factors of
5-100 improvement in energy-delay product, thereby enabling new
classes of portable and embedded applications.
Recent Publications
-
"Miss Tags for Fine-Grain CAM-Tag Cache Resizing"
Michael Zhang and Krste Asanovic
To appear, International Symposium on Low Power Electronics and Design,
Monterey, CA, August 2002.
-
"Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage
Reduction"
Seongmoo Heo and Krste Asanovic
(PDF paper)
VLSI Circuits Symposium, Honolulu, HI, June 2002.
-
"Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased
Bitlines"
(PDF paper)
Seongmoo Heo, Kenneth Barr, Mark Hampton, and Krste Asanovic
29th International Symposium on Computer Architecture
(ISCA-29), Anchorage, AK, May 2002.
-
"Direct Addressed Caches for Reduced Power Consumption"
Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanovic
(PDF paper)
34th International Symposium on Microarchitecture (MICRO-34),
Austin, TX, December 2001.
-
"The Span Cache: Software Controlled Tag Checks and Cache Line Size"
(PDF paper)
Emmett Witchel and Krste Asanovic
Workshop on Complexity-Effective Design, ISCA-28, Goteborg,
Sweden, June 2001.
-
"Way Memoization to Reduce Fetch Energy in Instruction Caches"
(PDF paper)
Albert Ma, Michael Zhang, and Krste Asanovic
Workshop on Complexity-Effective Design, ISCA-28, Goteborg,
Sweden, June 2001.
-
"Load-Sensitive Flip-Flop Characterization"
(PDF paper,
PDF slides,
PPT slides)
Seongmoo Heo and Krste Asanovic
IEEE Workshop on VLSI, Orlando, FL, April 2001.
-
"Activity-Sensitive Flip-Flop and Latch Selection for Reduced
Energy"
(PDF paper,
PDF slides,
PPT slides)
Seongmoo Heo, Ronny Krashinsky, and Krste Asanovic
19th Conference on Advanced Research in VLSI (ARVLSI'01),
Salt Lake City, UT, March 2001.
-
"Highly-Associative Caches for Low-Power Processors"
(PDF paper,
PDF slides,
PPT slides)
Michael Zhang and Krste Asanovic
Kool Chips Workshop, MICRO-33,
Monterey, CA, December 2000.
-
"Dynamic Zero Compression for Cache Energy Reduction"
(PDF paper,
PDF slides,
PPT slides)
Luis Villa, Michael Zhang, and Krste Asanovic
33rd International Symposium on Microarchitecture (MICRO-33),
Monterey, CA, December 2000.
"Energy-Efficient Register Access",
(PDF paper),
Jessica Tseng and Krste Asanovic,
SBCCI2000, XIII Symposium on Integrated Circuits and System Design,
Manaus, Amazonas, Brazil, September 2000.
-
"SyCHOSys: Compiled Energy-Performance Cycle Simulation"
(PDF paper,
PDF slides,
PowerPoint slides)
Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanovic
Workshop on Complexity-Effective Design, 27th International
Symposium on Computer Architecture, June 2000.
Recent Talks
[
MIT |
LCS |
CAG
]