Synthesizable Verilog MIPS Core
This is a synthesizable Verilog MIPS core that has been successfully mapped into FPGA and stdcell implementations. The core was originally written by Dan Rosenband with some minor mods by Ronny Krashinsky.
Warning: The directory is not well documented and the core is not actively supported.
- Verilog MIPS core, Core.tar.gz (29KB).