JTAG is an industry standard method of serially accessing signals or test points.  Originally JTAG was designed as a replacement for "bed of nails" circuit testers, as shrinking board geometries made such testers increasingly fragile and expensive.  More recently, JTAG is being incorporated in large chip designs as a way to independently test the chip subsystems by sensing and controlling signals at each subsystem boundary.

The JTAG specification does not limit its use to boundary connections, however.  Design-specific JTAG loops can access internal memories, override control signals or even initiate BIST sequences.

The JTAG interface provided on the tester baseboard consists of 5 signals:

	•	TCK - Test Clock.  The source for TCK will be either the adjustable onboard oscillator or a user-provided source.  TCK need not be synchronous with the D.U.T. clock, although it may be simplest to just use one clock.

	•	TMS - Test Mode Select.  The single control bit used to select the JTAG function.

	•	TDI - Test Data In.  A single data bit into the D.U.T.

	•	TDO - Test Data Out.  A single data bit out of the D.U.T.

	•	TRST - Test Reset.  This signal places the JTAG controller into a known initial state.

A white paper on JTAG by Sun Microsystems is available; also an online tutorial by Asset InterTech has additional information.

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The state diagram for JTAG control is shown here:

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