Rtst is a C library designed to aid in the testing of vector-matrix
A simple 5-stage pipeline MIPS core that has been successfully
synthesized into both FPGA and stdcell implementations.
SyCHOSys (Synchronous Circuit Hardware Orchestration System)
generates high-speed energy-performance cycle simulators by
compiling a processor description into efficient C++ code. This
framework can custom compile a cycle simulator with arbitrary
mixed levels of simulation detail ranging from gate-level to
purely behavioral models. In addition, SyCHOSys can compile
detailed energy statistics gathering code into the simulator and
generate a custom analysis tool to combine the resulting
statistics with capacitance values extracted from circuit layout
information to give energy dissipation.
SCALE Simulator Infrastructure
Simulator infrastructure used by SCALE group for architecture
research and chip design. Includes simulators for MIPS, SCALE, and the T0
vector microprocessor at the ISA, micro-architectural, and RTL
levels of abstraction.
Sive is an XML-Based configurable static design rule checker for
structural Verilog code. It uses a custom written iVerilog
target module to convert an input Verilog netlist into a simple
XML format. The netlist and a set of design rules are then used as
input to the actual sieve program. The sieve program verifies that
the design correctly follows the specified rules and outputs
information on any design rule violations.
Spongepaint is a new general purpose C++ framework for VLSI layout
which attempts to combine the convenience and flexibility of
automatic layout without sacrificing the control and quality of
manual layout. The framework includes support for Magic and GDS
file formats, virtual grid procedural layout, and standard cell
VISTA: Visualization Tool for Architects
A visualization framework written in Java that is tailored to
visualizing traces generated from architectural models at various
levels of abstraction. The framework uses modular and extendable
views to display trace data and currently supports a textual grid
view, waveform view, and pipeline view.
A cache energy-performance model for rapid exploration of the
low-power cache design space. Includes support for functional
cache simulation, as well as for more detailed cache simulation
based on practical RC delay models.
- IPM: Interval Performance Monitoring. Portable timing library.
- rprf: Portable performance measurement library (needs IPM).
We gratefully thank our past and present sponsors, including NSF,
DARPA, CMI, Project Oxygen, Epoch-IT, Infineon, Intel, and SGI.