This is an archive of the MIT SCALE group website.
SCALE was led by Prof. Krste Asanović, who joined the EECS Department at UC Berkeley in July 2007.

Computer Architecture Group
Computer Science and Artificial Intelligence Laboratory
Massachusetts Institute of Technology
The Stata Center, 32 Vassar Street, Cambridge, MA 02139, USA

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The SCALE group is developing technologies for future high-performance low-power computing systems. We take a cross-cutting approach, performing research at all system levels from compiler technology and computer architecture down to circuit design. Our recent application focus has been low-power processors for embedded devices.

Research Projects

The Scale Architecture

The Scale project is developing a new all-purpose programmable computing architecture for future system designs. Scale provides efficient support for all kinds of parallelism including data, thread, and instruction-level parallelism, and is intended to be competitive with custom ASICs in both performance and power.

Low-Power Microprocessor Design

We have been developing techniques that combine new circuit designs and microarchitectural algorithms to reduce both switching and leakage power in components that dominate energy consumption, including flip-flops, caches, datapaths, and register files.

Energy-Exposed Instruction Sets

Modern ISAs such as RISC or VLIW only expose to software properties of the implementation that affect performance. In this project we are developing new energy-exposed hardware-software interfaces that also allow software to have fine-grain control over energy consumption.

Mondriaan Memory Protection

Mondriaan memory protection (MMP) is a fine-grained protection scheme that allows multiple protection domains to flexibly share memory and export protected services. In contrast to earlier page-based systems, MMP allows arbitrary permissions control at the granularity of individual words.

Highly Parallel Memory Systems

We are investigating techniques for building high-performance, low-power memory subsystems for highly parallel architectures.

Transactional Memory

In many dynamic thread-parallel applications, lock management is the source of much programming complexity as well as space and time overhead. We are investigating possible practical microarchitectures for implementing transactional memory, which provides a superior solution for atomicity that is much simpler to program than locks, and which also reduces space and time overheads.

Mobile Computing Systems

Within the context of MIT Project Oxygen, several projects examine the energy and performance of complete mobile wireless systems.

Heads and Tails

Existing variable-length instruction formats provide higher code densities than fixed-length formats, but are ill-suited to pipelined or parallel instruction fetch and decode. Heads-and-Tails is a new variable-length instruction format that supports parallel fetch and decode of multiple instructions per cycle, allowing both high code density and rapid execution for high-performance embedded processors.


We gratefully thank our past and present sponsors, including NSF, DARPA, CMI, Project Oxygen, Epoch-IT, IBM, Infineon, Intel, Nokia, SGI, and Xilinx.