SCALE Group Publications and Talks

Many of these papers are copyright of the respective journal or conference organizing body. These online copies are provided for your personal research use only.

Categories

• Papers
• Book Chapters
• Theses
• Technical Reports and Memos
• Talks

Papers

• "Globally-Synchronized Frames for Guaranteed Quality-of-Service in On-Chip Networks"
  (PDF paper, PDF slides, PPT slides)
  Jae W. Lee, Man Cheuk Ng, and Krste Asanovic
  35th International Symposium on Computer Architecture (ISCA-35), Beijing, China, June 2008.

• "Compiling for Vector-Thread Architectures"
  (PDF paper)
  Mark Hampton and Krste Asanovic
  2008 International Symposium on Code Generation and Optimization (CGO), Boston, MA, April 2008.

• "Continual Hashing for Efficient Fine-Grain State Inconsistency Detection"
  (PDF paper)
  Jae W. Lee, Myron King, and Krste Asanovic
  25th IEEE International Conference on Computer Design (ICCD 2007), Lake Tahoe, CA, October 2007.

• "Energy Aware Lossless Data Compression"
  (PDF paper)
  Kenneth C. Barr and Krste Asanovic
  Transactions on Computer Systems, 24(3):250-291, Aug. 2006.

• "Implementing Virtual Memory in a Vector Processor with Software Restart Markers"
  (PDF paper, PDF slides, PPT slides)
  Mark Hampton and Krste Asanovic
  20th ACM International Conference on Supercomputing (ICS06), Cairns, Australia, June 2006.

• "METERG: Measurement-Based End-to-End Performance Estimation Technique in QoS-Capable Multiprocessors"
  (PDF paper, PDF slides)
  Jae W. Lee and Krste Asanovic
  12th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2006), San Jose, CA, April 2006.

• "Branch Trace Compression for Snapshot-Based Simulation"
  (PDF paper, PDF slides)
  Kenneth C. Barr and Krste Asanovic
  IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, March 2006.

• "Accelerating Architectural Exploration Using Canonical Instruction Segments"
  (PDF paper, PDF slides)
  Rose F. Liu and Krste Asanovic
  IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, March 2006.

• "Mondrix: Memory Isolation for Linux using Mondriaan Memory Protection"
  (PDF paper)
  Emmett Witchel, Junghwan Rhee, Krste Asanovic
  20th ACM Symposium on Operating Systems Principles (SOSP-20), Brighton, UK, October 2005.

• "Controlling Program Execution through Binary Instrumentation"
  (PDF paper)
  Heidi Pan, Krste Asanovic, Robert Cohn, and Chi-Keung Luk
  Workshop on Binary Instrumentation and Applications (WBIA-2005), 14th International Conference on Parallel Architectures and Compilation Techniques (PACT-14), St. Louis, MO, September 2005.

• "Replacing Global Wires with an On-Chip Network: A Power Analysis"
  (PDF paper)
  Seongmoo Heo and Krste Asanovic
  International Symposium on Low Power Electronics and Design (ISLPED'05), San Diego, CA, August 2005.

• "A Speculative Control Scheme for an Energy-Efficient Banked Register File"
  Jessica Tseng and Krste Asanovic
  IEEE Transactions on Computers, 54(6):741-751, June 2005.

• "Victim Replication: Maximizing Capacity while Hiding Wire Delay in Tiled CMPs"
  Michael Zhang and Krste Asanovic
  (PDF paper, PDF slides, PPT slides)
  32nd International Symposium on Computer Architecture (ISCA-32), Madison, WI, June 2005.

• "Accelerating Multiprocessor Simulation with a Memory Timestamp Record"
  (PDF paper, PDF slides)
  Kenneth C. Barr, Heidi Pan, Michael Zhang, and Krste Asanovic
  IEEE International Symposium on Performance Analysis of Systems and Software (ISPASS), Austin, TX, March 2005.

• "Unbounded Transactional Memory"
  (PDF paper)
  C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, and Sean Lie
  11th International Symposium on High Performance Computer Architecture (HPCA-11), San Francisco, CA, February 2005.

• "Minimizing Energy for Wireless Web Access with Bounded Slowdown"
  (PDF paper)
  Ronny Krashinsky and Hari Balakrishnan
  ACM/Kluwer Journal on Wireless Networks (WINET), Vol. 11, No. 1-2, pp. 135-148, January 2005.
  (Extended version of MobiCom 2002 paper)
  

• "Cache Refill/Access Decoupling for Vector Machines"
  (PDF paper, PDF slides, PDF slides+notes)
  Christopher Batten, Ronny Krashinsky, Steve Gerding, and Krste Asanovic
  37th International Symposium on Microarchitecture (MICRO-37), Portland, OR, December 2004.

• "The Vector-Thread Architecture"
  (PDF paper)
  Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, and Krste Asanovic
  IEEE Micro Special Issue: Micro's Top Picks from Computer Architecture Conferences, November/December 2004.
  (Abridged version of ISCA 2004 paper)

• "Power-Optimal Pipelining in Deep Submicron Technology"
  (PDF paper, PDF slides, PPT slides)
  Seongmoo Heo and Krste Asanovic
  International Symposium on Low Power Electronics and Design (ISLPED'04), Newport Beach, CA, August 2004.

• "The Vector-Thread Architecture"
  (PDF paper, PDF slides, PPT slides)
  Ronny Krashinsky, Christopher Batten, Mark Hampton, Steve Gerding, Brian Pharris, Jared Casper, and Krste Asanovic
  31st International Symposium on Computer Architecture (ISCA-31), Munich, Germany, June 2004.

• "Reducing Power Density through Activity Migration"
  (PDF paper, PDF slides, PPT slides)
  Seongmoo Heo, Ken Barr, and Krste Asanovic
  International Symposium on Low Power Electronics and Design (ISLPED), Seoul, Korea, August 2003.

• "Banked Multiported Register Files for High-Frequency Superscalar Microprocessors"
  (PDF paper, PDF slides, PPT slides)
  Jessica Tseng and Krste Asanovic
  30th International Symposium on Computer Architecture (ISCA-30), San Diego, CA, June 2003.

• "Hardware Works, Software Doesn't: Enforcing Modularity with Mondriaan Memory Protection"
  (PDF paper, PDF slides, PPT slides)
  Emmett Witchel and Krste Asanovic
  9th Workshop on Hot Topics in Operating Systems (HotOS-IX), Lihue, HI, May 2003.

• "Energy Aware Lossless Data Compression"
  (PDF paper, PPT Slides)
  Kenneth Barr and Krste Asanovic
  Best Paper, First International Conference on Mobile Systems, Applications, and Services (MobiSys-2003) , San Francisco, CA, May 2003.

• "Mondrian Memory Protection"
  (PDF paper, PPT slides, PDF slides)
  Emmett Witchel, Josh Cates, and Krste Asanovic
  Tenth International Conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-X) , San Jose, CA, October 2002.

• "Minimizing Energy for Wireless Web Access with Bounded Slowdown"
  (PDF paper, PDF slides, PPT slides, simulation code)
  Ronny Krashinsky and Hari Balakrishnan
  MobiCom 2002, Atlanta, GA, September 2002.
  (Subsequent versions published in WINET 2005, see above)
  

• "Miss Tags for Fine-Grain CAM-Tag Cache Resizing"
  (PDF paper, PPT slides)
  Michael Zhang and Krste Asanovic
  International Symposium on Low Power Electronics and Design (ISLPED-2002), Monterey, CA, August 2002.

• "Leakage-Biased Domino Circuits for Dynamic Fine-Grain Leakage Reduction"
  Seongmoo Heo and Krste Asanovic
  (PDF paper, PPT slides, PDF slides)
  VLSI Circuits Symposium, Honolulu, HI, June 2002.

• "Dynamic Fine-Grain Leakage Reduction Using Leakage-Biased Bitlines"
  (PDF paper, PPT slides, PDF slides)
  Seongmoo Heo, Kenneth Barr, Mark Hampton, and Krste Asanovic
  29th International Symposium on Computer Architecture (ISCA-29), Anchorage, AK, May 2002.

• "Direct Addressed Caches for Reduced Power Consumption"
  Emmett Witchel, Sam Larsen, C. Scott Ananian, and Krste Asanovic
  (PDF paper, PDF slides, )
  34th International Symposium on Microarchitecture (MICRO-34), Austin, TX, December 2001.

• "Heads and Tails: A Variable-Length Instruction Format Supporting Parallel Fetch and Decode"
  (PDF paper, PDF slides, PPT slides)
  Heidi Pan and Krste Asanovic
  International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES 2001), Atlanta, GA, November 2001.

• "Multithreading Decoupled Architectures for Complexity-Effective General Purpose Computing"
  (PDF paper)
  Michael Sung, Ronny Krashinsky, and Krste Asanovic
  Workshop on Memory Access Decoupled Architectures (MEDEA'01), PACT'01, Barcelona, Spain, September 2001.
  (Also appears in) Computer Architecture News, 29(5), December 2001.

• "The Span Cache: Software Controlled Tag Checks and Cache Line Size"
  (PDF paper)
  Emmett Witchel and Krste Asanovic
  Workshop on Complexity-Effective Design, ISCA-28, Goteborg, Sweden, June 2001.

• "Way Memoization to Reduce Fetch Energy in Instruction Caches"
  (PDF paper)
  Albert Ma, Michael Zhang, and Krste Asanovic
  Workshop on Complexity-Effective Design, ISCA-28, Goteborg, Sweden, June 2001.

• "Load-Sensitive Flip-Flop Characterization"
  (PDF paper, PDF slides, PPT slides)
  Seongmoo Heo and Krste Asanovic
  IEEE Workshop on VLSI, Orlando, FL, April 2001.

• "Activity-Sensitive Flip-Flop and Latch Selection for Reduced Energy"
  (PDF paper, PDF slides, PPT slides)
  Seongmoo Heo, Ronny Krashinsky, and Krste Asanovic
  19th Conference on Advanced Research in VLSI (ARVLSI'01), Salt Lake City, UT, March 2001.

• "Highly-Associative Caches for Low-Power Processors"
  (PDF paper, PDF slides, PPT slides)
  Michael Zhang and Krste Asanovic
  Kool Chips Workshop, MICRO-33, Monterey, CA, December 2000.

• "Dynamic Zero Compression for Cache Energy Reduction"
  (PDF paper, PDF slides, PPT slides)
  Luis Villa, Michael Zhang, and Krste Asanovic
  33rd International Symposium on Microarchitecture (MICRO-33), Monterey, CA, December 2000.

• "Energy-Efficient Register Access"
  (PDF paper, PDF slides, PPT slides)
  Jessica Tseng and Krste Asanovic
  XIII Symposium on Integrated Circuits and System Design (SBCCI2000), Manaus, Amazonas, Brazil, September 2000.

• "SyCHOSys: Compiled Energy-Performance Cycle Simulation"
  (PDF paper, PDF slides, PPT slides)
  Ronny Krashinsky, Seongmoo Heo, Michael Zhang, and Krste Asanovic
  Workshop on Complexity-Effective Design, ISCA-27, Vancouver, BC, Canada, June 2000.

• "Energy-Exposed Instruction Set Architectures"
  (PDF abstract, PDF slides)
  Krste Asanovic
  Work In Progress Session, HPCA-6, Toulouse, France, January 2000.

Book Chapters

• "Energy-Exposed Instruction Sets"
  (PDF paper, Book Website)
  Krste Asanovic, Mark Hampton, Ronny Krashinsky, and Emmett Witchel
  Power Aware Computing, Robert Graybill and Rami Melhem (Eds.), Kluwer Academic/Plenum Publishers, June 2002.

PhD Theses

• Reducing Exception Management Overhead with Software Restart Markers
  (PDF paper)
  Mark Hampton
  Ph.D. dissertation, Massachusetts Institute of Technology, February, 2008.

• Vector-Thread Architecture and Implementation
  (PDF paper)
  Ronny Krashinsky
  Ph.D. dissertation, Massachusetts Institute of Technology, June, 2007.
  Winner, George M. Sprowls Award for best Ph.D. theses in computer science, MIT, 2007.
  

• Summarizing Multiprocessor Program Execution with Versatile, Microarchitecture-Independent Snapshots
  (PDF paper, PDF slides)
  Kenneth C. Barr
  Ph.D. dissertation, Massachusetts Institute of Technology, September, 2006.

• Circuits for High-Performance Low-Power VLSI Logic
  (PDF paper)
  Albert Ma
  Ph.D. dissertation, Massachusetts Institute of Technology, May, 2006.

• Banked Microarchitectures for Complexity-Effective Superscalar Microprocessors
  (PDF paper)
  Jessica Hui-Chun Tseng
  Ph.D. dissertation, Massachusetts Institute of Technology, May, 2006.

• "Latency Reduction Techniques for Chip Multiprocessor Cache Systems"
  (PDF paper)
  Michael Zhang
  Ph.D. dissertation, Massachusetts Institute of Technology, January, 2006.

• "Optimal Digital System Design in Deep Submicron Technology"
  (PDF paper)
  Seongmoo Heo
  Ph.D. dissertation, Massachusetts Institute of Technology, January, 2006.

• "Mondriaan Memory Protection"
  (PDF paper)
  Emmett Witchel
  Ph.D. dissertation, Massachusetts Institute of Technology, January, 2004.
  Winner, George M. Sprowls Award for best Ph.D. theses in computer science, MIT, 2004.
  Received Honorable Mention in ACM Distinguished Dissertation Awards 2004.

Masters Theses

• "The Extreme Benchmark Suite: Measuring High-Performance Embedded Systems"
  (PDF)
  Steven Gerding
  S.M. Thesis, Massachusetts Institute of Technology, September 2005.

• "SCALE DRAM Subsystem Power Analysis"
  (PDF)
  Vimal Bhalodia,
  M.Eng. Thesis, Massachusetts Institute of Technology, September 2005.

• "AXCIS: Rapid Processor Architectural Exploration using Canonical Instruction Segments"
  (PDF)
  Rose F. Liu
  M.Eng. Thesis, Massachusetts Institute of Technology, September 2005.

• "Fast Fourier Transform on a 3D FPGA"
  (PDF)
  Elizabeth A. Basha
  S.M. Thesis, Massachusetts Institute of Technology, September 2005.

• "The SCALE DRAM Subsystem"
  (PDF)
  Brian Pharris
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2004.

• "Hardware Support for Unbounded Transactional Memory"
  (PDF)
  Sean Lie
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2004.

• "EProf: An Energy Profiler for the iPAQ"
  (PDF)
  Kelly Koskelin
  M.Eng. Thesis, Massachusetts Institute of Technology, February 2004.

• "VISTA: A Visualization Tool for Computer Architects"
  (PDF)
  Aaron D. Mihalik
  M.Eng. Thesis, Massachusetts Institute of Technology, January 2004.

• "Sieve: An XML-Based Structural Verilog Rules Check Tool"
  (PDF)
  Tina Cheng
  M.Eng. Thesis, Massachusetts Institute of Technology, August 2003.

• "ZOOM: A Performance-Energy Cache Simulator"
  (PDF)
  Regina Sam
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.

• "Low-Power Single-Precision IEEE Floating-Point Unit"
  (PDF)
  Sheetal Jain
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.

• "Video Over IP: An Example Reconfigurable Computing Application for a Handheld Device"
  (PDF)
  Elina Kamenetskaya
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2003.

• "Energy Aware Lossless Data Compression"
  (PDF)
  Kenneth C. Barr
  S.M. Thesis, Massachusetts Institute of Technology, September 2002.

• "High-Performance Variable-Length Instruction Encodings"
  (PDF)
  Heidi Pan
  M.Eng. Thesis, Massachusetts Institute of Technology, June 2002.
  Winner, Charles and Jennifer Johnson Award for best M.Eng. thesis in computer science, MIT, 2002.

• "Exposing Datapath Elements to Reduce Microprocessor Energy Consumption"
  (PDF)
  Mark Hampton
  S.M. Thesis, Massachusetts Institute of Technology, June 2001.

• "Microprocessor Energy Characterization and Optimization through Fast, Accurate, and Flexible Simulation"
  (PDF)
  Ronny Krashinsky
  S.M. Thesis, Massachusetts Institute of Technology, May 2001.

• "A Low-power 32-bit Datapath Design"
  (PDF)
  Seongmoo Heo
  S.M. Thesis, Massachusetts Institute of Technology, August 2000.

• "A Procedural Layout Library in Java"
  (PDF)
  Gong Ke Shen
  M.Eng. Thesis, Massachusetts Institute of Technology, May 2000.

• "Energy-Efficient Register File Design"
  (PDF)
  Jessica Tseng
  S.M. Thesis, Massachusetts Institute of Technology, December 1999.

• "Reducing Instruction Cache Energy Using Gated Wordlines"
  (PDF files: Cover, Abstract, Contents, Text)
  Mukaya Panich
  M.Eng. Thesis, Massachusetts Institute of Technology, August 1999.

Technical Reports and Memos

• "Scale Control Processor Test-Chip"
  (PDF paper)
  Christopher Batten, Ronny Krashinsky, and Krste Asanovic
  MIT CSAIL Technical Report, MIT-CSAIL-TR-2007-003, January 2007.

• "RingScalar: A Complexity-Effective Out-of-Order Superscalar Microarchitecture"
  (PDF paper)
  Jessica Tseng and Krste Asanovic
  MIT CSAIL Technical Report, MIT-CSAIL-TR-2006-066, September 2006.

• "Victim Migration: Dynamically Adapting Between Private and Shared CMP Caches"
  (PDF paper)
  Michael Zhang and Krste Asanovic
  MIT CSAIL Technical Report, MIT-CSAIL-TR-2005-064 (MIT-LCS-TR-1005), October 2005.

• "Dynamically Resizable Static CMOS Logic for Fine-Grain Leakage Reduction"
  (PDF paper)
  Seongmoo Heo and Krste Asanovic
  MIT LCS Technical Report, MIT-LCS-TR-957, July 2004.

• "Versatility and VersaBench: A New Metric and a Benchmark Suite for Flexible Architectures"
  (PDF paper) Rodric M. Rabbah, Ian Bratt, Krste Asanovic, and Anant Agarwal, MIT CSAIL Technical Memo, MIT-LCS-TM-646, June 2004

• "A Double-Pulsed Set-Conditional-Reset Flip-Flop"
  (PDF paper)
  Albert Ma and Krste Asanovic
  MIT LCS Technical Report, MIT-LCS-TR-844, May 2002.

Talks

• "The Vector-Thread Architecture"
  (PowerPoint slides, PDF slides)
  Boston Area Architecture Workshop (BARC), January 30, 2003.
  

• "10 ways to cheat with energy"
  (PDF slides, PowerPoint slides)
  Metrics workshop, DARPA PAC/C Kickoff meeting, May 24, 2000.

• "PACE: Power-Aware Computing Engines"
  (PDF slides, PowerPoint slides)
  DARPA PAC/C Kickoff meeting, May 24, 2000.

• "Energy-Efficient Memory Systems"
  (PDF slides)
  DARPA visit with Malleable Cache group, September 21, 1999.

• "SCALE intro"
  (PDF slides)
  DARPA visit, April 28, 1999.